COMSOL 6.4 - Surface Trapping in a Silicon Nanowire Gate-All-Around Device

Surface Trapping in a Silicon Nanowire Gate-All-Around Device

This example demonstrates the use of various traps. In particular the effect of gate field screening by surface trap charges is studied. A nanoscale gate-all-around MOSFET is modeled and the shift of turn-on voltage due to the screening effect is computed.

Surface traps can have important effects on the operation of many semiconductor devices. These traps are associated with donor and acceptor atoms, with other impurity atoms, or with “dangling bonds” that occur at defects or exterior surfaces and grain boundaries. It is useful to consider the processes that can occur when trap states at a given energy, Et, exchange electrons or holes with states in the valence or conduction bands at energy E. This situation is shown in Figure 1. There are four processes that occur, corresponding to the emission and capture of both electrons and holes between states in the bands

Figure 1: The four processes that contribute to SRH recombination. Left: An electron in the conduction band with energy E is captured by a trap with energy Et (ec). Center left: An electron in a trap at energy Et is emitted to an empty state with energy E in the conduction band (ee). Center right: An electron in a trap at energy Et moves to an empty state in the valence band at energy E. Equivalently a hole in the valence band is trapped (hc). Right: An electron from an occupied state in the valence band at energy E is excited into a trap with energy Et. Equivalently a hole in the trap is emitted (he).

In practice one may want to consider a set of discrete trap levels or a continuum of trap states (with a density of states gt(Et)). Both of these approaches are possible in the Semiconductor Module, but in this model a discrete set of traps is considered, with trap density per unit area Nt at a trap energy, Et.

For the trap energy Et, carriers in the conduction band or valence band with energy E make the following contributions to the total recombination or generation rate per unit area for each process:

where Nt is the number of traps per area and cec(E), cee(E) chc(E) and che(E) are rate constants. The net rate of capture for electrons and holes in the energy interval dE can be written as:

(1)

In thermal equilibrium the principle of detailed balance implies the reversibility of each microscopic process that leads to equilibrium. Consequently at equilibrium the expressions in the square brackets must be equal to zero. This leads to the following relationships between the rate constants:

In thermal equilibrium the occupancy of the electron traps fte are determined by Fermi Dirac statistics, fte=1/[1 + exp(Et − Ef)/gD] (where gD is the degeneracy factor). The above equations can therefore be simplified to yield:

(2)

Equation 2 applies even away from equilibrium. Substituting this equation back into Equation 1, rearranging and integrating, gives the total rate of electron (re) or hole (rh) capture to traps at the specified energy, Et:

where the quasi-Fermi levels have been introduced.

Introducing the constants Cn and Cp, which represent the average capture probability of an electron over the band:

and noting that:

the following equations are obtained:

(3)

where:

(4)

Equation 3 and Equation 4 define the electron and hole recombination rates associated with the trap energy level. The total rate of change of the number of trapped electrons is given by:

(5)

Equation 5 determines the occupancy of the traps at the level Et.

The total surface recombination rate for electrons and holes is given by summing over the distinct discrete traps (denoted by the superscript i), giving the following result:

Finally the charge resulting from the occupied traps must also be computed. In general the charge on a trap site depends on the nature of the trap. Table 1 summarizes the different trap types currently included in the Semiconductor Module.

Table 1: Charge due to different types of trap.
Trap type	Species trapped	Charge occupied	Charge unoccupied	Number density
Donor trap	Electron	0	+
Acceptor trap	Hole	0	-
Neutral electron trap	Electron	-	0
Neutral hole trap	Hole	+	0

The total number of traps at the discrete level Ei is:

The total charge density, Q, that results from the traps is given by:

(6)

Equation 6 can be rewritten in the form:

where E0 is an energy within the band gap referred to as the neutral level. E0 is chosen such that:

So if a neutral energy is employed the following equation applies for the charge on the traps:

(7)

A neutral level is often a convenient way of characterizing a set of traps at a boundary, because the details of the types of trapping sites are frequently not known. However, it is possible to assign a neutral level to the boundary using experimental techniques such as capacitance measurements. In this model the neutral level is assumed to be below the midgap, whilst the traps are assumed to be at the midgap. This means that only the first term on the right-hand side of Equation 7 applies.

Model Definition

The nanoscale gate-all-around MOSFET is modeled as a simple cylinder of 10 nm radius in 2D axisymmetric geometry (see Figure 2). The 100 nm long silicon channel is p-doped at a concentration level of 1·1017 cm−3. The 10 nm long drain and source regions are n-doped at a concentration level of 1·1020 cm−3. Figure 3 shows the overall signed doping profile. The gate with a 2 nm thick oxide layer and surface traps is modeled using the thin insulator gate boundary condition around the perimeter of the channel. The source boundary is grounded and the drain is set at 0.5 V; both with ideal ohmic contacts. The gate voltage is swept from −0.5 to 1.5 V at 0.1 V intervals, for three different surface trap densities: 0.1·1012, and 5·1012 cm−2.

Figure 2: Geometry.

Figure 3: Doping profile.

Results and Discussion

The computed current–voltage curves for the three trap densities are shown in Figure 4 in semi-log scale. The higher turn-on voltages for higher densities of surface traps is a direct result of the screening effect of the surface trap charges, as discussed in the next few paragraphs.

Figure 4: Current vs gate voltage.

Figure 5 shows the relevant energy levels along the radius at the central cross section of the silicon channel when the MOSFET is in the ON state, for the case of trap density of 5·1012 cm−2 and gate voltage of 1.5 V. The main effect of the gate voltage is to pull the conduction band (blue curve) below the electron quasi-Fermi level (red curve), leading to an increase in the electron density (and thus the current density) underneath the gate.

Figure 5: Conduction band (blue), valence band (green), electron quasi-Fermi level (red) and hole quasi-Fermi level (cyan) along the radius at the central cross section of the silicon channel when the MOSFET is in the on state, for the case of a trap density of 5·1012cm−2 and a gate voltage of 1.5 V.

Figure 6 shows, from left to right, the current density, the hole concentration (log scale), the electron concentration (log scale), and the electric field, when the MOSFET is in the on state, for the case of trap density of 5·1012 cm−2 and gate voltage of 1.5 V. The hole concentration is much lower than the electron concentration. Thus it does not contribute to the conduction current. The increase in the electron concentration and current density beneath the gate surface is clearly seen.

Figure 6: From left to right, the current density, the hole concentration (log scale), the electron concentration (log scale), and the electric field, when the MOSFET is in the ON state, for the case of trap density of 5·1012 cm−2 and gate voltage of 1.5 V.

Figure 7 illustrates the screening effect by plotting the electric potential along the radius at the central cross section of the channel, for the gate voltage of 1.5V. The blue, green, and red curves are for the trap densities of 0.1·1012, and 5·1012 cm−2, respectively. The electric potential is pulled down further by higher concentrations of surface traps, leading to less pileup and higher turn-on voltage.

Figure 7: Electric potential along the radius at the central cross section of the channel, for the gate voltage of 1.5V. The blue, green, and red curves are for the trap concentrations of 0, 1·1012, and 5·1012cm−2, respectively.

Figure 8 shows the trap occupancy fraction along the length of the channel, at three gate voltages for the trap density of 5·1012 cm−2. At the gate voltage of −0.5 V, the occupancy is less than 10% in the central portion of the channel. At 0 V (still below turn-on), it is about 90%, and quickly rises to 100% in the ON state.

Figure 8: Trap occupancy fraction along the length of the channel, at three gate voltages for the trap density of 5·1012cm−2.

Semiconductor_Module/Transistors/nanowire_traps

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Name	Expression	Value	Description
Rw	10[nm]	1E-8 m	Nanowire radius
L	100[nm]	1E-7 m	Gate length
t_ox	2[nm]	2E-9 m	Oxide thickness
t_np	Rw	1E-8 m	Additional length
Na_0	1e17[1/cm^3]	1E23 1/m³	Background acceptor concentration
Nd_0	1e20[1/cm^3]	1E26 1/m³	Maximum donor concentration
Nt_0	1e10[1/cm^2]	1E14 1/m²	Trap density
Vd	500[mV]	0.5 V	Drain voltage
Vg	-500[mV]	-0.5 V	Gate voltage
ramp	1	1	Ramp parameter