COMSOL 6.4 - Programming of a Floating Gate EEPROM Device

Programming of a Floating Gate EEPROM Device

This model calculates the current and charge characteristics of a floating gate Electrically Erasable Programmable Read-Only Memory (EEPROM) device. A stationary study computes the current–voltage response of the device for a charged and uncharged floating gate. This demonstrates how the state of the memory can be read via measurements of the device resistance. Time dependent studies are then used to simulate the effects of transient voltage pulses on the control gate. These pulses cause current to tunnel between the floating gate and the semiconductor material, allowing charge to be stored or removed from the floating gate. A write-erase cycle is performed, where charge is first stored on the floating gate by an initial voltage pulse before a subsequent pulse discharges the device, returning it to its original state.

Introduction

EEPROM devices are the building blocks of modern nonvolatile memory, which is becoming an increasingly important storage medium for computers and mobile devices. The structure of an EEPROM device is similar to that of a MOSFET, except that the single gate contact is replaced by two electrically isolated gates: a floating gate and a control gate (see Figure 1).

Figure 1: Model geometry showing key components of the EEPROM. The tunnel barrier is highlighted in blue.

The floating gate is electrically isolated from the rest of the device and a fixed charge is applied to it, which indicates the state of the memory. During normal operation, the control gate is used in a similar manner to the gate in a MOSFET device; its potential controls the channel width. However, the field applied to the channel depends on the charge stored on the floating gate, so at a fixed control gate bias the channel resistance varies depending on the charge applied to the floating gate (see Figure 4 below).

For this device, charge is added to the floating gate (known as programming) by applying a high field to the device (hot carrier injection is also used for this process in some EEPROM devices). The geometry of the floating gate is such that the electric field is concentrated in a small region immediately over a heavily doped part of the drain contact (known as the tunnel implant). In this region the electric field exceeds the threshold for a process known as Fowler–Nordheim tunneling, in which electrons tunnel directly into the conduction band of the insulator. For the silicon–silicon oxide system only the electron tunneling is significant and the tunnel current is given by:

where Eins is the electric field in the insulator, and

and

are constants related to the material properties of the insulator and semiconductor (see Ref. 1 for details). As current flows into the floating gate as a result of the applied field the charge on the gate builds up and this in turn acts to oppose the applied field. Thus the charging of the floating gate is a self-limiting process for a fixed applied bias, similar in nature to the charging of a capacitor through a resistor.

The device presented here is based on that described in Ref. 2.

Model Definition

The model structure is shown in Figure 1. The device has a total length of 1.8 μm with a channel length, the distance between the highly doped n-type regions, of 0.55 μm. The source and drain contacts are 0.2 μm deep, with a shallower 0.1 μm deep tunnel implant protruding 0.25 μm from the drain region. The floating gate is separated from the channel by a 50 nm thick oxide layer, however directly above the tunnel implant the oxide thickness is only 8 nm. This 8 nm region serves a tunnel barrier between the MOSFET-like semiconductor device and the floating gate. When a voltage is applied to the control gate, the geometry of the floating gate serves to concentrate the resulting electric field in the region of the tunnel barrier. This can be seen in Figure 2, which shows the electric field during the programming voltage pulse. Sufficiently large control voltages generate an electric field capable of causing electron tunneling across the tunnel barrier.

Figure 2: Surface plot showing the electric field during the control voltage pulse used to program the EEPROM device. Note how the field is concentrated in the region of the tunnel barrier.

The first study demonstrates the effect of varying the charge stored on the floating gate. For this study, the source and base contacts are grounded and a fixed voltage of 10 mV is applied to the drain. For two different values of stored charge, 0 and −2×10-15 C, the control gate voltage is swept from 0 to 3 V. The source current is plotted as a function of the control gate voltage for both values of stored charge.

The next two studies perform a program and erase cycle. As with the first study, the source and base contacts are grounded and a fixed voltage of 10 mV is applied to the drain. A time dependent voltage pulse is applied to the control gate, this pulse has positive sign for the program event and negative sign for the erase event, as shown below in Figure 3. For the duration of the voltage pulse electrons tunnel across the tunnel barrier. The positive program pulse causes electrons to accumulate on the floating gate. The subsequent negative pulse causes these electrons to tunnel back out again returning the floating gate near to its initial zero charge configuration. Note that the program event uses a solution from the first study as the initial condition; the erase event then takes the “programmed” state from the program event study as its initial condition.

Figure 3: Time dependent control voltage pulses used for the program and erase event studies.

Results and Discussion

Figure 4 shows the current–voltage characteristics of the device for two different values of charge stored on the floating gate. As expected, the device behaves like a MOSFET, with no current flowing between the source and drain until a threshold “turn-on” control voltage is reached. This is because at the threshold voltage the electric field induces a thin inversion layer, in which the semiconductor changes from p-type to n-type, opening a conducting channel between the source and drain regions. As the control voltage increases past the threshold the width of the conducting channel increases, reducing the resistance between the source and drain contacts and allowing more current to flow for a given source–drain voltage. The stored charge changes the turn-on voltage, resulting in a different source–drain resistance for a given control voltage. By measuring the current at a given control and drain voltage it is thus possible to tell is charge is stored on the floating gate. For example, setting the control voltage to 1 V would result in no current if the device is in the erased configuration (zero stored charge) but approximately 0.5 μA if the device was charged to −2·10−15 C.

Figure 4: Source current as a function of control voltage for a fixed drain voltage of 10 mV. The blue line shows the curve when the device is in the erased state (zero stored charge). The green line shows the curve when the device is in the programmed state.

Figure 5 shows the tunnel current as a function of time throughout the program and erase events. During the program event electrons tunnel onto the floating gate, resulting in a conventional current with negative sign. When electrons tunnel back out of the floating gate during the erase event there is a positive current of equal magnitude to the program event.

Figure 6 shows the charge stored on the floating gate as a function of time throughout the program and erase events. As the charge is due to electrons tunneling through the tunnel barrier, the program event results in the accumulation of a negative charge on the floating gate and the erase event returns the charge to near zero.

Figure 5: Tunnel current as a function of time for the program and erase events.

Figure 6: Charge on the floating gate as a function of time throughout the program and erase events.

References

1. M. Lenzlinger and E. H. Snow, “Fowler-Nordheim Tunneling into Thermally Grown SiO2,” J. Applied Physics, vol. 40, no. 1, pp. 278–283, 1969.

2. A. Concannon, S. Keeney, A. Mathewson, and C. Lombardi, “Two-Dimensional Numerical Analysis of Floating-Gate EEPROM Devices,” IEEE Transactions on Electron Devices, vol. 40, no. 7, pp. 1258–1262, 1993.

Semiconductor_Module/Transistors/eeprom

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Property	Variable	Value	Unit	Property group
Relative permittivity	epsilonr_iso ; epsilonrii = epsilonr_iso, epsilonrij = 0	4.2	1	Basic

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Name	Expression	Value	Description
Qgate	0[C]	0 C	Gate charge
Vcontrol	0.1[V]	0.1 V	Control voltage
Vd	10[mV]	0.01 V	Drain voltage
Vmax	23.7[V]	23.7 V	Transient voltage maximum
A_fn	1.23e-6[A/V^2]	1.23E-6 A/V²	A tunneling coefficient
B_fn	237[MV/cm]	2.37E10 V/m	B tunneling coefficient